Automatic test pattern generation (ATPG) is used to identify test sequences which can be applied to circuits to determine whether they operate correctly. In ATPG, test patterns are generated and used to test semiconductor devices after manufacture. Test patterns may also be used to assist in the determination of the causes of defects.
Effective testing of integrated circuits (ICs) significantly enhances the ability of IC developers and manufacturers to provide reliable devices. Various techniques have been employed to test res during the manufacturing process. One such technique that is commonly known, and has been used within the industry for over twenty years is scan testing.
Scan testing provides an efficient approach to testing the structural integrity of devices, such as flip-flops, within a complex IC. Scan testing does not test integrated circuit-level functionality. Rather, test personnel use scan testing to confirm that individual flip-flops within an IC function properly. The number of flip-flops within an IC, which is often greater than a million, presents a challenge for testing. Scan testing addresses this challenge through the use of automated test units that provide test vectors to scan paths including thousands of flip-flops within ICs that have been designed to support scan testing.
Typically, complex ICs are designed and implemented as a series of interconnected functional blocks, each of which can be tested independently. Devices, such as flip-flops, within these functional blocks can be designed, such that they can be connected together in a scan path to support scan testing. Flip-flops and other elements within a scan path include, in addition to inputs and outputs used for normal operation, two inputs associated with the scan testing capability. These include a scan input (SI) and a scan enable (SE) input. Flip-flops within a scan path have their output connected to the SI input of a subsequent flip-flop. The first flip-flop within a scan path receives its input from an automated test unit through a test access port on the chip. The last flip-flop within a scan path provides its output to the automated test unit through a test access port. Many scan paths can exist within a single IC.
While scan testing provides significant benefits, challenges exist related to compression. A compression architecture generally includes a decompressor receiving test input bit streams from a set of pins to load the plurality of scan chains. The IC is tested with the scan chains and produces corresponding test output bit streams. A compressor receives the test output bit streams and compresses it in a scan output that is compared to a predicted pattern to determine whether an error occurred during testing.
The scan compression factor is increasing, e.g. 60-80× is becoming common. There is a demand to go beyond 100× and beyond. For most of the designs with high compression, the Quality of Results (QoR) is not as expected, e.g. coverage drop greater than 1% is common. And, real compression may be very low due to pattern inflation, e.g. about 3-5× with respect to internal scan mode. QoR may also be affected by the increase in dependency at the input side, and/or fault masking at the output side.
Referring to FIGS. 1A, 1B, 1C and 2, existing scan compression testing approaches will be discussed. FIGS. 1A, 1B and 1C schematically illustrate a portion of a scan compression architecture 10 including scan paths (e.g. columns 1-8) of flip-flops FF that are input (e.g. via inputs X and Y, and data selectors M) with values (i.e. 1s and 0s) according to selected test patterns and within modes (e.g. Modes 00, 01, 10 etc.). Such approaches include a horizontal dependency (e.g. within a row) on the values loaded into the scan paths (e.g. repeating 0 and 1 in the rows in Mode 00, or repeating 0, 0, 1, 1 in the rows of Mode 01 etc.). Two scan paths may be forced to have the same load value and possibly the same unload value, and due to the compression (e.g. using XOR gates), the resulting data does not indicate which scan path includes a faulty flip-flop. This defeats the goals of compression because the number of patterns may need to be increased to achieve the desired results.
FIG. 2 illustrates an example of an adaptive mode scan compression architecture 20 that includes the use of data selectors M (or MUXs) that are controlled to vary the mode of scan compression during the test (e.g. at each clock pulse) as the load values are shifted through the scan path of flip-flops FF. This may reduce some horizontal dependency but requires more complex control and interpretation of results.
These discussed problems are common in designs with high compression and negatively affect coverage and compression factor. Real compression is low compared to implemented compression. To compensate the loss of coverage, incremental patterns are generated in internal scan mode. Scan length is huge is internal scan mode and increases test time and test data volume heavily (i.e. overall compression goes further down).